1. Technical Field
The present invention relates to a high-capacity auxiliary memory and, in particular, to a memory device with a small computer system interface (SCSI).
2. Related Art
A common electronic private branch exchange (PBX) system uses a hard disk as a memory device for storing a program and a database. Such a hard disk is independently connected to the exchange system, and serves as an auxiliary memory device for providing the exchange system with the necessary program and database. Specifically, the hard disk is connected to a main module of the exchange system via a small computer system interface (hereinafter referred to as SCSI).
In the case where the exchange system uses a mechanically-driven memory device (i.e., a hard disk is used as the high-capacity auxiliary memory device), it takes a long time to read and write data. Further, reliability of data reading and writing operations becomes lower and the life span of the hard disk becomes shorter.
The following patents are considered to be representative of the prior art, and are burdened by the disadvantages set forth herein: U.S. Pat. No.5,682,497 to Robinson, entitled Managing File Structures For A Flash Memory File System In A Computer, U.S. Pat. No. 5,644,539 to Yamagami et al., entitled Storage Device Employing A Flash memory, U.S. Pat. No. 5,668,957 to Davis et al., entitled Method And Apparatus For Providing Virtual DMA Capability On An Adapter Connected To A Computer System BUS With No DMA Support, U.S. Pat. No. 5,640,349 to Kakinuma et al., entitled Flash Memory System, U.S. Pat. No. 5,631,745 to Wong et al., entitled Multi-Function Telecommunications Instrument, U.S. Pat. No. 5,603,056 to Totani, entitled Disk Drive Control Computer And Method For Rewriting Control Program In Flash EEPROM With Serial Communication Using Unassigned Pins Of SCSI Or ATA Connector, U.S. Pat. No. 5,603,001 to Sukegawa et al., entitled Semiconductor Disk System Having Plurality Of Flash Memories, U.S. Pat. No. 5,581,723 to Hasbun et al., entitled Method And Apparatus For Retaining Flash Block Structure Data During Erase Operations In A Flash EEPROM Memory Array, U.S. Pat. No. 5,581,503 to Matsubara et al., entitled Data Line Disturbance Free Memory Block Divided Flash Memory And Microcomputer Having Flash Memory Therein, U.S. Pat. No. 5,572,466 to Sukegawa, entitled Flash Memory Chips, U.S. Pat. No. 5,530,828 to Khaki et al., entitled Semiconductor Storage Device Including A Controller For Continuously Writing Data To And Erasing Data From A Plurality Of Flash Memories, U.S. Pat. No. 5,528,758 to Yeh, entitled Method And Apparatus For Providing A Portable Computer With Integrated Circuit (IC) Memory Card Storage In Custom And Standard Formats, U.S. Pat. No. 5,199,033 to McGeoch et al., entitled Solid State Memory Array Using Address Block Bit Substitution To Compensate For Non-Functional Storage Cells, U.S. Pat. No. 5,509,134 to Fandrich et al., entitled Method And Apparatus For Execution Of Operations In A Flash Memory Array, U.S. Pat. No. 5,530,673 to Tobita et al., entitled Flash Memory Control Method And Information Processing System Therewith, U.S. Pat. No. 5,428,755 to Imai et al., entitled Method For Automatically Modifying Program In A Flash Memory Of A Magnetic Tape Unit, U.S. Pat. No. 5,046,086 to Bergen et al., entitled Page-Mapped Multi-Line Telephone Communication Systems, U.S. Pat. No.5,191,556 to Radjy, entitled Method Of Page-Mode Programming Flash EEPROM Cell Arrays, U.S. Pat. No. 4,979,171 to Ashley, entitled Announcement And Tone Code Generator For Telephonic Network And Method, U.S. Pat. No.5,373,466 to Landeta et al., entitled Flash-Clear of RAM Array Using Partial Reset Mechanism, U.S. Pat. No. 5,410,511 to Michiyama, entitled Method of Controlling the Erasing and Writing of Information in Flash Memory, U.S. Pat. No. 5,280,454 to Tanaka et al., entitled Electrically Erasable Programmable Read-Only Memory with Block-Erase Function, U.S. Pat. No. 5,337,281 to Kobayashi et al., entitled Non-Volatitle Semiconductor Memory Device in Which Data can be Erased on a Block Basis and Method of Erasing Data on a Block Basis in Non-Volatile Semiconductor Memory Device, U.S. Pat. No. 5,414,664 to Lin et al., entitled Flash EPROM with Block Erase Flags for Over-Erase Protection, U.S. Pat. No. 5,596,530 to Lin et al., entitled Flash EPROM with Block Erase Flags for Over-Erase Protection, U.S. Pat. No. 5,544,103 to Lambertson, entitled Compact Page-Erasable EEPROM Non-Volatile Memory, and U.S. Pat. No. 5,355,347 to Cioaca, entitled Single Transistor per EEPROM Memory Device with bit Line Sector Page Programming.